1. Field of the Invention
This invention relates to computer systems. In particular, the invention relates to emulation of microprocessor instructions.
2. Description of Related Art
When a processor is improved to incorporate enhanced capabilities, it is important to maintain software compatibility with the applications developed in the previous model. One particular problem is the representation of data for logical and/or arithmetic operations.
For example, the floating-point (FP) number format has a single-precision (SP) and double-precision (DP) data formats. While the SP format is typically represented by a 32-bit representation, the DP format may have two different types of representation: a regular 64-bit format and an expanded 82-bit format. A regular processor typically uses the regular 64-bit FPDP format for operands stored both in its registers and in memory. An enhanced processor typically uses the expanded 82-bit FPDP format for operands stored in its registers and the regular 64-bit FPDP format for operands stored in the memory. For example, the Intel Architecture (IA) processors have a 32-bit model and an enhanced 64-bit model: the IA-32 processor and the IA-64 processor. The IA-32 processor uses the 64-bit FPDP format for operands stored in both registers and memory. The IA-64 processor uses the 64-bit FPDP format for memory operands and the expanded 82-bit FPDP format for register operands.
The transition from one instruction set operating with a regular data format to another instruction set operating with an enhanced data format is referred to as an instruction set architecture (ISA) transition. On such an ISA transition where an application program written using a regular mode of operation (e.g., 64-bit FPDP) is transported to a processor using the enhanced mode of operation (e.g., 82-bit FPDP), or vice versa, operand mismatches may occur. Such mismatches cause performance degradation and in many cases may cause software incompatibility.
Therefore, there is a need in the technology to provide a method to emulate an instruction set for one data format on a processor that operates in an expanded data format.